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? 1990, 1993, 1994 data sheet mos integrated circuit m pd43256b 256k-bit cmos static ram 32k-word by 8-bit description the m pd43256b is a high speed, low power, and 262, 144 bits (32,768 words by 8 bits) cmos static ram. battery backup is available (l, ll, a, and b versions). and a and b versions are wide voltage operations. the m pd43256b is packed in 28-pin plastic dip, 28-pin plastic sop and 28-pin plastic tsop (i). features ? 32,768 words by 8 bits organization ? fast access time: 70, 85, 100, 120, 150 ns (max.) ? wide voltage range (a version: v cc = 3.0 to 5.5 v, b version: v cc = 2.7 to 5.5 v) ? 2 v data retention ? oe input for easy application access time operating operating standby data retention part number ns (max.) supply voltage temperature supply current supply current note 1 v c m a (max.) m a (max.) m pd43256b-l 70, 85 4.5 to 5.5 0 to 70 50 3 m pd43256b-ll 70, 85 15 2 m pd43256b-a 85, 100 note 2 , 120 note 2 3.0 to 5.5 m pd43256b-b note 2 100, 120, 150 2.7 to 5.5 notes 1. t a 40 ?c, v cc = 3 v 2. access time : 85 ns (max.) (v cc = 4.5 to 5.5 v) version x and p this data sheet can be applied to the version x and p. each version is identified with its lot number. letter x in the fifth character position in a lot number signifies version x, letter p, version p. the information in this document is subject to change without notice. the mark shows major revised points. document no. m10770ej9v0ds00 (9th edition) date published may 1997 n printed in japan d43256b japan lot number
2 m pd43256b ordering information access time operating operating part number package ns (max.) supply voltage temperature remark v?c m pd43256bcz-70l 28-pin plastic 70 4.5 to 5.5 0 to 70 l version m pd43256bcz-85l dip (600 mil) 85 m pd43256bcz-70ll 70 ll version m pd43256bcz-85ll 85 m pD43256BGU-70l 28-pin plastic 70 l version m pD43256BGU-85l sop (450 mil) 85 m pD43256BGU-70ll 70 ll version m pD43256BGU-85ll 85 m pD43256BGU-a85 85 3.0 to 5.5 a version m pD43256BGU-a10 100 m pD43256BGU-a12 120 m pD43256BGU-b10 100 2.7 to 5.5 b version m pD43256BGU-b12 120 m pD43256BGU-b15 150 m pd43256bgw-70ll-9jl 28-pin plastic 70 4.5 to 5.5 ll version m pd43256bgw-85ll-9jl tsop (i) 85 m pd43256bgw-a85-9jl (8 13.4 mm) 85 3.0 to 5.5 a version m pd43256bgw-a10-9jl (normal bent) 100 m pd43256bgw-a12-9jl 120 m pd43256bgw-b10-9jl 100 2.7 to 5.5 b version m pd43256bgw-b12-9jl 120 m pd43256bgw-b15-9jl 150 m pd43256bgw-70ll-9kl 28-pin plastic 70 4.5 to 5.5 ll version m pd43256bgw-85ll-9kl tsop (i) 85 m pd43256bgw-a85-9kl (8 13.4 mm) 85 3.0 to 5.5 a version m pd43256bgw-a10-9kl (reverse bent) 100 m pd43256bgw-a12-9kl 120 m pd43256bgw-b10-9kl 100 2.7 to 5.5 b version m pd43256bgw-b12-9kl 120 m pd43256bgw-b15-9kl 150
3 m pd43256b pin configuration (marking side) a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we a13 a8 a9 a11 oe a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 28-pin plastic dip (600 mil) pd43256bcz 28-pin plastic sop (450 mil) pD43256BGU m m a0 - a14 : address inputs i/o1 - i/o8 : data inputs/outputs cs : chip select we : write enable oe : output enable v cc : power supply gnd : ground
4 m pd43256b 1 28-pin plastic tsop (i) (8 13.4 mm) (normal bent) pd43256bgw-9jl m 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 oe a11 a9 a8 a13 we v cc a14 a12 a7 a6 a5 a4 a3 1 28-pin plastic tsop (i) (8 13.4 mm) (reverse bent) pd43256bgw-9kl m 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 oe a11 a9 a8 a13 we v cc a14 a12 a7 a6 a5 a4 a3
5 m pd43256b block diagram a0 | a14 i/o1 | i/o8 address buffer row decoder memory cell array 262,144 bits input data controller sense/switch column decoder address buffer output data controller cs oe v cc we gnd truth table cs oe we mode i/o supply current h not selected high impedance i sb l h h output disable i cca l l write d in l l h read d out remark : dont care
6 m pd43256b electrical characteristics absolute maximum ratings parameter symbol rating unit supply voltage v cc C0.5 note to +7.0 v input/output voltage v t C0.5 note to v cc + 0.5 v operating ambient temperature t a 0 to 70 ?c storage temperature t stg C55 to +125 ?c note C3.0 v (min.) (pulse width 50 ns) caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational sections of this characteristics. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol m pd43256b-l m pd43256b-a m pd43256b-b unit m pd43256b-ll min. max. min. max. min. max. supply voltage v cc 4.5 5.5 3.0 5.5 2.7 5.5 v high level input voltage v ih 2.2 v cc + 0.5 2.2 v cc + 0.5 2.2 v cc + 0.5 v low level input voltage v il C0.3 note +0.8 C0.3 note +0.5 C0.3 note +0.5 v operating ambient temperature t a 070070070?c note C3.0 v (min.) (pulse width 50 ns)
7 m pd43256b dc characteristics (recommended operating conditions unless otherwise noted) (1/2) parameter symbol test conditions m pd43256b-l m pd43256b-ll unit min. typ. max. min. typ. max. input leakage current i li v in = 0 v to v cc C1.0 +1.0 C1.0 +1.0 m a i/o leakage current i lo v i/o = 0 v to v cc C1.0 +1.0 C1.0 +1.0 m a oe = v ih or cs = v ih or we = v il operating supply current i cca1 cs = v il , minimum cycle time, 45 45 ma i i/o = 0 ma i cca2 cs = v il , i i/o = 0 ma 10 10 i cca3 cs 0.2 v, cycle = 1 mhz, 10 10 i i/o = 0 ma v il 0.2 v, v ih v cc C 0.2 v standby supply current i sb cs = v ih 33ma i sb1 cs v cc C 0.2 v 1.0 50 0.5 15 m a high level output voltage v oh1 i oh = C1.0 ma 2.4 2.4 v v oh2 i oh = C0.1 ma v cc C0.5 v cc C0.5 low level output voltage v ol i ol = 2.1 ma 0.4 0.4 v remarks 1. v in : input voltage 2. these dc characteristics are in common regardless of package types.
8 m pd43256b dc characteristics (recommended operating conditions unless otherwise noted) (2/2) parameter symbol test conditions m pd43256b-a m pd43256b-b unit min. typ. max. min. typ. max. input leakage current i li v in = 0 v to v cc C1.0 +1.0 C1.0 +1.0 m a i/o leakage current i lo v i/o = 0 v to v cc C1.0 +1.0 C1.0 +1.0 m a cs = v ih or we = v il or oe = v ih operating supply current i cca1 cs = v il , m pd43256b-a85 45 ma minimum cycle time, m pd43256b-a10 i i/o = 0 ma m pd43256b-a12 m pd43256b-b10 45 m pd43256b-b12 m pd43256b-b15 v cc 3.3 v 20 i cca2 cs = v il , i i/o = 0 ma 10 10 v cc 3.3 v 5 i cca3 cs 0.2 v, cycle = 1 mhz, 10 10 i i/o = 0 ma, v il 0.2 v, v ih v cc C 0.2 v v cc 3.3 v 5 standby supply current i sb cs = v ih 33ma v cc 3.3 v 2 i sb1 cs v cc C 0.2 v 0.5 15 0.5 15 m a v cc 3.3 v 0.5 10 high level output voltage v oh1 i oh = C1.0 ma, v cc 4.5 v 2.4 2.4 v i oh = C0.5 ma, v cc < 4.5 v 2.4 2.4 v oh2 i oh = C0.1 ma i oh = C0.02 ma v cc C0.1 v cc C0.1 low level output voltage v ol i ol = 2.1 ma, v cc 4.5 v 0.4 0.4 v i ol = 1.0 ma, v cc < 4.5 v 0.4 0.4 v ol1 i ol = 0.02 ma 0.1 0.1 remarks 1. v in : input voltage 2. these dc characteristics are in common regardless of package types. capacitance (t a = 25 ?c, f = 1 mhz) parameter symbol test conditions min. typ. max. unit input capacitance c in v in = 0 v 5 pf input/output capacitance c i/o v i/o = 0 v 8 pf remarks 1. v in : input voltage 2. these parameters are periodically sampled and not 100 % tested.
9 m pd43256b ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions input waveform (rise/fall time 5 ns) input pulse levels 0.8 v to 2.2 v: m pd43256b-l, 43256b-ll 0.5 v to 2.2 v: m pd43256b-a, 43256b-b 1.5 v 1.5 v test points output waveform 1.5 v 1.5 v test points output load m pd43256b-a, 43256b-b : 1ttl + 100 pf m pd43256b-l, 43256b-ll: ac characteristics with notes should be measured with the output load shown in figure 1 and figure 2 . figure 1 figure 2 (for t aa , t acs , t oe , t oh ) (for t chz , t clz , t ohz , t olz , t whz , t ow ) +5 v i/o (output) 1.8 k w 100 pf c l 990 w +5 v i/o (output) 1.8 k w 5 pf c l 990 w remark c l includes capacitances of the probe and jig, and stray capacitances.
10 m pd43256b read cycle (1/2) v cc 4.5 v m pd43256b-85 parameter symbol m pd43256b-70 m pd43256b-a85/a10/a12 unit condition m pd43256b-b10/b12/b15 min. max. min. max. read cycle time t rc 70 85 ns address access time t aa 70 85 ns note 1 cs access time t acs 70 85 ns oe access time t oe 35 40 ns output hold from address change t oh 10 10 ns cs to output in low impedance t clz 10 10 ns note 2 oe to output in low impedance t olz 55ns cs to output in high impedance t chz 30 30 ns oe to output in high impedance t ohz 30 30 ns notes 1. see the output load shown in figure 1 except for m pd43256b-a, 43256b-b. 2. see the output load shown in figure 2 except for m pd43256b-a, 43256b-b. remark these ac characteristics are in common regardless of package types and l, ll versions. read cycle (2/2) v cc 3.0 v v cc 2.7 v parameter symbol m pd43256b-a85 m pd43256b-a10 m pd43256b-a12 m pd43256b-b10 m pd43256b-b12 m pd43256b-b15 unit min. max. min. max. min. max. min. max. min. max. min. max. read cycle time t rc 85 100 120 100 120 150 ns address access time t aa 85 100 120 100 120 150 ns note cs access time t acs 85 100 120 100 120 150 ns oe access time t oe 50 60 60 60 60 70 ns output hold from address change t oh 10 10 10 10 10 10 ns cs to output in low impedance t clz 10 10 10 10 10 10 ns oe to output in low impedance t olz 555 555ns cs to output in high impedance t chz 35 35 40 35 40 50 ns oe to output in high impedance t ohz 35 35 40 35 40 50 ns note loading condition is 1ttl + 100 pf. remark these ac characteristics are in common regardless of package types and l, ll versions. con- dition
11 m pd43256b read cycle timing chart remark in read cycle, we should be fixed to high level. t rc t aa t acs t clz t oe t olz t ohz t chz t oh address (input) cs (input) oe (input) i/o (output) high impedance high impedance data out
12 m pd43256b write cycle (1/2) v cc 4.5 v m pd43256b-85 parameter symbol m pd43256b-70 m pd43256b-a85/a10/a12 unit condition m pd43256b-b10/b12/b15 min. max. min. max. write cycle time t wc 70 85 ns cs to end of write t cw 50 70 ns address valid to end of write t aw 50 70 ns write pulse width t wp 55 60 ns data valid to end of write t dw 30 35 ns data hold time t dh 00ns address setup time t as 00ns write recovery time t wr 00ns we to output in high impedance t whz 30 30 ns note output active from end of write t ow 10 10 ns note see the output load shown in figure 2 except for m pd43256b-a, 43256b-b. remark these ac characteristics are in common regardless of package types and l, ll versions. write cycle (2/2) v cc 3.0 v v cc 2.7 v parameter symbol m pd43256b-a85 m pd43256b-a10 m pd43256b-a12 m pd43256b-b10 m pd43256b-b12 m pd43256b-b15 unit min. max. min. max. min. max. min. max. min. max. min. max. write cycle time t wc 85 100 120 100 120 150 ns cs to end of write t cw 70 70 90 70 90 100 ns address valid to end of write t aw 70 70 90 70 90 100 ns write pulse width t wp 60 60 80 60 80 90 ns data valid to end of write t dw 60 60 70 60 70 80 ns data hold time t dh 000 000ns address setup time t as 000 000ns write recovery time t wr 000 000ns we to output in high impedance t whz 30 35 40 35 40 50 ns note output active from end of write t ow 10 10 10 10 10 10 ns note loading condition is 1ttl + 100 pf. remark these ac characteristics are in common regardless of package types and l, ll versions. con- dition
13 m pd43256b write cycle timing chart 1 (we controlled) t wc t cw t aw t wp t as t wr t whz t dw t dh t ow indefinite data out high impe- dance high impe- dance data in indefinite data out address (input) cs (input) we (input) i/o (input/output) cautions 1. cs or we should be fixed to high level during address transition. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remarks 1. write operation is done during the overlap time of a low level cs and a low level we. 2. when we is at low level, the i/o pins are always high impedance. when we is at high level, read operation is executed. therefore oe should be at high level to make the i/o pins high impedance. 3. if cs changes to low level at the same time or after the change of we to low level, the i/o pins will remain high impedance state.
14 m pd43256b write cycle timing chart 2 (cs controlled) t wc t as t cw t aw t wp t wr t dw t dh data in high impedance address (input) cs (input) we (input) i/o (input) high impedance cautions 1. cs or we should be fixed to high level during address transition. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remark write operation is done during the overlap time of a low level cs and a low level we.
15 m pd43256b low v cc data retention characteristics l version ( m pd43256b-l: t a = 0 to 70 ?c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v ccdr cs v cc C 0.2 v 2.0 5.5 v data retention supply current i ccdr v cc = 3.0 v, cs v cc C 0.2 v 0.5 20 note m a chip deselection to data t cdr 0ns retention mode operation recovery time t r 5ms note 3 m a (t a 40 ?c) ll version ( m pd43256b-ll: t a = 0 to 70 ?c) a version ( m pd43256b-a: t a = 0 to 70 ?c) b version ( m pd43256b-b: t a = 0 to 70 ?c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v ccdr cs v cc C 0.2 v 2.0 5.5 v data retention supply current i ccdr v cc = 3.0 v, cs v cc C 0.2 v 0.5 7 note m a chip deselection to data t cdr 0ns retention mode operation recovery time t r 5ms note 2 m a (t a 40 ?c), 1 m a (t a 25 ?c)
16 m pd43256b data retention timing chart t cdr data retention mode t r 5.0 v 4.5 v v ccdr v il (max.) gnd note cs v cc ?0.2 v v ih (min.) cs v cc note a version: 3.0 v, b version: 2.7 v remark the other pins (address, oe, we, i/os) can be in high impedance state.
17 m pd43256b package drawings 28 pin plastic dip (600 mil) item millimeters inches a b c f g h i j k 38.10 max. 2.54 (t.p.) 3.6?.3 0.51 min. 4.31 max. 2.54 max. l 0.25 15.24 (t.p.) 5.72 max. 13.2 n 1.2 min. 1.500 max. 0.100 max. 0.047 min. 0.142?.012 0.020 min. 0.170 max. 0.226 max. 0.600 (t.p.) 0.520 0.01 0.100 (t.p.) p28c-100-600a1-1 d 0.50?.10 0.020 m 0.25 0.010 +0.10 ?.05 r 0 ~ 15 ? 0 ~ 15 ? +0.004 ?.005 +0.004 ?.003 notes each lead centerline is located within 0.25 mm (0.01 inch) of its true position (t.p.) at maximum material condition. item "k" to center of leads when formed parallel. 1) 2) 28 1 15 14 a m r k l b i j g h c f d m n
18 m pd43256b 28 15 1 14 n c d m m i a h p f g e b l j k note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 28 pin plastic sop (450 mil) p28gu-50-450a-1 item millimeters inches a b c d e f g h i j 19.05 max. 1.27 (t.p.) 3.0 max. 2.55?.1 11.8?.3 1.27 max. k l 0.12 0.7?.2 1.7?.2 8.4?.1 0.20 m 0.10 0.40?.10 0.2?.1 n +0.07 ?.03 0.750 max. 0.050 max. 0.016 0.008?.004 0.119 max. 0.100 0.465 0.331 0.067?.008 0.008 0.028 0.005 0.004 +0.008 ?.009 0.050 (t.p.) p 55? 55? +0.004 ?.005 +0.005 ?.004 +0.012 ?.013 +0.004 ?.005 +0.003 ?.002 detail of lead end
19 m pd43256b 28pin plastic tsop ( i ) (8 13.4) item millimeters inches note (1) each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. p28gw-55-9jl-1 m 0.08 0.003 n 0.10 0.004 h 12.4?.2 0.488?.008 i 11.8?.1 0.465 +0.004 ?.005 j 0.8?.2 0.031 +0.009 ?.008 s 1.2 max. 0.048 max. a 8.0?.1 0.315?.004 b 0.6 max. 0.024 max. c 0.55 (t.p.) 0.022 (t.p.) g 1.0 0.039 k 0.145 0.006?.001 l 0.5?.1 0.020 +0.004 ?.005 p 13.4?.2 0.528 +0.008 ?.009 q 0.1?.05 0.004?.002 r 3 ? +7 ? ? ? 3 ? +7 ? ? ? d 0.22 0.009?.003 +0.08 ?.07 m detail of lead end q r g b c d m j n l k +0.025 ?.015 1 14 28 15 s a p i h (2) "a" excludes mold flash. (includes mold flash : 8.4mm max. <0.331 inch max.>)
20 m pd43256b 28pin plastic tsop ( i ) (8 13.4) item millimeters inches note p28gw-55-9kl-1 m 0.08 0.003 n 0.10 0.004 h 12.4?.2 0.488?.008 i 11.8?.1 0.465 +0.004 ?.005 j 0.8?.2 0.031 +0.009 ?.008 s 1.2 max. 0.048 max. a 8.0?.1 0.315?.004 b 0.6 max. 0.024 max. c 0.55 (t.p.) 0.022 (t.p.) g 1.0 0.039 k 0.145 0.006?.001 l 0.5?.1 0.020 +0.004 ?.005 p 13.4?.2 0.528 +0.008 ?.009 q 0.1?.05 0.004?.002 r 3 ? +7 ? ? ? 3 ? +7 ? ? ? d 0.22 0.009?.003 +0.08 ?.07 detail of lead end r q b c d j n l k +0.025 ?.015 m m g 1 14 28 15 s a p i h (1) each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. (2) "a" excludes mold flash. (includes mold flash : 8.4mm max. <0.331 inch max.>)
21 m pd43256b recommended soldering conditions the following conditions (see table below) must be met when soldering m pd43256b. for more details, refer to our document semiconductor device mounting technology manual (c10535e) . please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. types of surface mount device m pD43256BGU: 28-pin plastic sop (450 mil) m pd43256bgw-9jl: 28-pin plastic tsop (i) (8 13.4 mm) (normal bent) m pd43256bgw-9kl: 28-pin plastic tsop (i) (8 13.4 mm) (reverse bent) please consult with our sales offices. type of through hole mount device m pd43256bcz: 28-pin plastic dip (600 mil) soldering process soldering conditions wave soldering solder temperature: 260 ?c or below, (only to leads) flow time: 10 seconds or below partial heating method terminal temperature: 300 ?c or below, time: 3 seconds or below (per one lead) caution do not jet molten solder on the surface of package.
22 m pd43256b [memo]
23 m pd43256b notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
2 m pd43256b [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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